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14th IEEE International Conference on Advanced Thermal Processing of Semiconductors
RTP 2006
October 10 - 13, 2006
Brighton Hotel, Kyoto,
Japan
IEEE Catalog Number:06EX1530
ISBN:1-4244-0648-X
Library of Congress:2006932759
- Process-Integration Challenges with up-to-date Modulation of Scaling Laws
S. Nakai, Fujitsu, Japan
Presentation Slides
- Growing Importance of Fundamental Understanding on the Source
of Process Variations
S. Sato, NEC Yamagata, Japan
Presentation Slides
- Laser Annealing Technology and Device Integration Challenges
A. Shima, Hitachi, Tokyo, Japan
Presentation Slides
- Influence of the Atmosphere on Ultra-Thin Oxynitride Film for
Precisely Controlled Plasma Nitridation Process
K. Saki, M. Tamaoki, T. Shimizu, S. Ito, S. Mori, A. Shimizaki,
I. Mizushima, A. Yamamoto, Toshiba, Japan
Presentation Slides
- Double-Pulsed Laser Annealing Technologies and Related Applications
T. Kudo, Sumimoto Heavy Industries, Kanagawa, Japan
Presentation Slides
- Ni-silicide/Si and SiGe(C) Contact Technology for ULSI Applications
O. Nakatsuka, S. Zaima, A. Sakai, M. Ogawa, Nagoya University, Japan
Presentation Slides
- Ultra-shallow Junction Formation by Plasma Doping and Flash Lamp Annealing
K. Tsutsui, K. Majima, Y. Fugakawa, K. Kakushima, Tokyo Institute of
Technology, Yokohama, Japan
Y. Sasaki, C-G. Jim, H. Ito, B. Mizuno, Ultimate Junction Technologies, Osaka, Japan
H. Iwai, H. Sauddin, P. Ahmet, Frontier Collaborative Research Center,
Tokyo Institute of Technology, Yokohama, Japan
Presentation Slides
- Millisecond Annealing with Flashlamps: Tool and Process Challenges
T. Gebel, L. Rebohle, R. Fendler, W. Hentsch, FHR Anlagebau, Ottendorf-Okrilla
W. Skorupa, M. Voelskow, W. Anwand, R. A. Yankov, Forschungszentrum Rossendorf
Presentation Slides
- The Progress in Ultra Thin Gate Dielectric for System LSI Application
J. Yugami, S. Tsujikawa, M. Inoue, M. Mizutani, T. Hayashi, Y. Nishida, H. Umeda,
Renesas Technology, Hyogo, Japan
Presentation Slides
-
Flash Lamp Annealing Latest Technology for 45nm Device and Future Devices
H. Kiyama, Dainippon Screen, Japan
Presentation Slides
- Process Integration Issues with Spike, Laser and Flash Anneal Implementation
for 90 and 65nm Technologies
Th. Feudel, M. Horstmann, L. Herrmann, M. Herden, M. Gerhardt, D. Greenlaw,
AMD Saxony, Dresden, Germany
P. Fisher, J. Kluth, AMD Corporation/IBM, Hopewell Junction, USA
Presentation Slides
- Ultra-Shallow Junction Formed by Plasma Doping and Laser Annealing
S. Heo, H. Hwang, GIST, Gwang-Ju, Korea
Presentation Slides
- Kinetics of Shallow Junction Formation: Physical Mechanisms
Hal Kennel, M.D. Giles, M. Diebel, P.H. Keys, J. Hwang, S. Govindaraju,
M. Liu, A. Budrevich, Intel, Hillsboro, USA
Presentation Slides
- Mechanical Stress in Silicon Based Materials: Evolution Upon Annealing
and Impact on Device Performance
P. Morin, STMicroelectronics, Crolles, France
Presentation Slides
- Flash Annealing Technology for USJ: Modeling and Metrology
J. Gelpey, S. McCoy, D. Camm, Mattson Technology Canada, Vancouver, Canada
W. Lerch, S. Paul, Mattson Thermal Products, Dornstadt, Germany
P. Pichler, Fraunhofer IISB, Erlangen, Germany
J. O. Borland, JOB Consulting, Aiea, USA
P. Timans, Mattson Technology, Fremont, USA
Presentation Slides
- Fundamental Mechanisms for Reduction of Leakage Current of Silicon
Oxide and Oxynitride through RTP-Induced Phonon-Energy Coupling
Z. Chen, J. Guo, P. Ong, University of Kentucky, Lexington, USA
Presentation Slides
- Non-Destructive Characterization of Metal-Semiconductor Interfaces
by Raman Scattering
H. Harima, Kyoto Institute of Technology, Kyoto, Japan
Presentation Slides
High-Resolution Transmission Electron Microscopy of Interfaces between Thin Nickel
Layers on Si(001) after Nickel Silicide Formation under Various Annealing Conditions
T. Isshiki, K. Nishio, T. Sasaki, H. Harima, M. Yoshimoto, Kyoto Institute
of Technology, Kyoto, Japan
T. Fukada, W. S. Yoo WaferMasters, San Jose, USA
- NBTI Immune First Plasma Nitridation SiON with Multiple Single-Wafer Tools
for 45nm node Gate Dielectrics
M. Tanaka, S. Koyama, E. Hasegawa, S. Shishiguchi, M. Hane, NEC Kanagawa, Japan
C. Olsen, Applied Materials, Santa Clara, USA
Presentation Slides
Non-contact, Non-destructive Crystal Quality Characterization of Ultra-shallow
Ion Implanted Silicon Wafers before and after Annealing
M. Yoshimoto, H. Nishigaki, H. Harima, T. Isshiki, Kyoto Institute
of Technology, Kyoto, Japan
K. Kang, W. S. Yoo, WaferMasters, San Jose, USA
- Thermal Controllability of High Temperature (> 1400 oC) Rapid Thermal
Oxidation for SiC MOSFET
S. Ogata, T. Oka, ULVAC, Kanagawa, Japan
K. Tsuda, M. Nakayama, ULVAC-RIKO, Kanagawa, Japan
R. Kosugi, National Institute of Advanced Industrial Science and Technology (AIST),
Tsukuba Ibaraki, Japan
Presentation Slides
- Sub-30nm MOSFET Fabrication Technology Incorporating Precise Dopant Profile
Design Using Diffusion-less High-Activation Laser Annealing
M. Narihiro, T. Iwamoto, T. Yamamoto, T. Ikezawa, K. Yakoh, M. Tanaka,
A. Mineji, Y. Okuda, K. Uejima, S. Shishiguchi, M. Hane, NEC, Kanagawa, Japan
Presentation Slides
Micro-scale Sheet Resistance Measurement on Ultra Shallow Junctions
C. L. Petersen, R. Lin, P.F. Nielsen, CAPRES A/S Burnabay, Canada
D. Petersen, CAPRES A/S Lingby, Denmark
Rapid Thermal Processing Strategies for Highly Uniform and Repeatable Process
Results on Patterned Wafers
Woo Sik Yoo, WaferMasters, San Jose, USA
- Pattern Effects with the Mask Off…
Z. Nenyei, J. Niess, W. Lerch, W. Dietl Mattson Thermal Products, Dornstadt, Germany
P. Timans, Mattson Technology, Fremont, USA
P. Pichler, Fraunhofer IISB, Erlangen, Germany
Presentation Slides
- Deep Melt Laser Thermal Annealing for Power Field Effect Transistor
T. Gutt, Infenion Technologies, Neubiberg, Germany
H. Schulze, T. Rupp, Germany, Infenion Technologies, Austria
J. Venturini, SOPRA, Gennevilliers, France
Presentation Slides
RTP Diffusion and Junction formation in Si, GaAs and InP
S. Shishiyanu, Technical University of Moldova, Chisinau, Moldova
- Low Thermal Budget Activation of B in Si
H. Bourdon, A. Halimaoui, A. Talbot, D. Dutartre, STMicroelectronics, Crolles, France
J. Venturini, SOPRA, Gennevilliers, France
O. Marcelot, CEMES, Toulouse, France
Presentation Slides
- Raman Study on the Process of Si Advanced Integrated Circuits
S. Nishibe, T. Sasaki, H. Harima, Kyoto Institute of Technology, Kyoto, Japan
K. Kisoda, Wakayama University, Wakayama, Japan
T. Yamazaki, W. S. Yoo, WaferMasters, San Jose, USA
Presentation Slides
- Raman Study of Low-Temperature Formation of Nickel-Silicide Layers
T. Sasaki, S. Nishibe, H. Harima, T. Isshiki, M. Yoshimito, Kyoto Institute
of Technology, Kyoto, Japan
K. Kisoda, Wakayama University, Japan
W. S. Yoo, T. Fukada, WaferMasters, San Jose, CA
Presentation Slides
- Laser Annealed Ni(Ti) Silicides Formation
Y. Setiawan, P.S. Lee, K. L. Pey, X.C. Wang, G. C. Lim, NTU, Singapore
F. L. Chow, Chartered Semiconductor Manufacturing, Woodland Industrial Park, Singapore
Presentation Slides
Cobalt Silicide Formation Characteristics in a Single Wafer Rapid Thermal
Furnace (SRTF) System
D. Erbetta, T. Marangon, STMicroelectronics, Agrate Brianza, Italy
T. Ueda, T. Fukada, M. Ouaknine, I. J. Malik, W. S. Yoo, WaferMasters, San Jose, USA
- Impact of Ni Layer Thickness and Anneal Time on Nickel Silicide Formation
By Rapid Thermal Processing
T. Huelsmann, J. Niess, W. Lerch, Mattson Thermal Products, Dornstadt, Germany
O. Fursenko, D. Bolze, IHP, Im Technologiepark, Frankfurt (Oder), Germany
Presentation Slides
Changes in Optical Properties during Nickel Silicide Formation and Potential
Impact on Process Results using Various Heating Methods
W. S. Yoo, T. Fukada, I. J. Malik, WaferMasters, San Jose, USA
- Optimization of Annealing for ClusterBoron® and ClusterCarbon™ PMOS SDE
K. Sekar, W. Krull, SemEquip, Inc., North Billerica, USA
K. Verheyden, K. Funk, ASM Europe, Almere, The Netherlands
Presentation Slides
Titanium Silicide Formation: Process Characterization of Single Wafer Rapid
Thermal Furnace System
D. Garroux, Altis Semiconductor, Corbeil Essonnes, France
M. Ouaknine , I. Malik, T. Fukada, T. Ueda, M. Odera, T. Ishigaki,
T. Ueda, W. S. Yoo, WaferMasters, San Jose, USA
- Improvement of Within Wafer Uniformity of Device Parameters by Gradient
Temperature Control with Bell Jar Type Hot Wall RTP
K. W. Lee, S. Kim, P. Frisella, B. Jacobs, G. Cai, R. Reece, Axcelis Beverley, USA
N. Y. Kwak, C. Y. Ham, K. C. Joo, D. H. Lee, S. W. Park, S. K. Park, Hynix Semiconductor,
Kyungki-do, Korea
Presentation Slides
- Device Scaling Effest on the Spectral Absorptance of Wafer Front Side
267
K. Fu, Yu-Bin Chen, Pei-feng Hsu, Florida Institute of Technology, Melbourne, USA
Z.M. Zhang, Woodruff School of Mechanical Engineering
Georgia Institute of Technology, Atlanta, USA
Presentation Slides
- Insertion Error in LPRT Temperature Measurements
Y. Qu, E. Puttitwong, J. R. Howell, O. A. Ezekoye, The University of Texas, Austin, USA
Presentation Slides
Hot Plate Emissivity Effect in Low Temperature Annealing
T. Fukada, W. S. Yoo, WaferMasters, San Jose, USA
- Calibration of Low Temperature Cable-Less Lightpipe Pyrometer
on the NIST PEB Test Bed Between 50 oC and 225 oC
B. K. Tsai, K. G. Kreider, W. A. Kimes, NIST, Gaithersburg, USA
Presentation Slides