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5th International Conference on Advanced Thermal Processing of Semiconductors

RTP 1997

September 3 - September 5, 1997

New Orleans Hilton Riverside

New Orleans, Louisiana

 

Wednesday, September 3, 1997

PLENARY SESSION

 

Technology and Reliability of Ultrathin Gate and Tunneling Dielectrics

H.Z. Massoud, Duke University, Raleigh, NC, H.H. Heinisch, W.K. Henson, B.E. Hornung, E.M. Vogel, J.J. Wortman, North Carolina State University, Raleigh, NC

Ultrathin Nitrided-Oxide Gate Dielectrics Prepared by RTP for ULSI Application.

T. Hori, Matsushita, Kyoto, Japan

Furnace and Clean Technology for Improved EEPROM Tunnel Oxide Quality and Charge Retention.

J.F. Buller, Advanced Micro Devices, Austin, TX, S. Fong, Advanced Micro Devices, Sunnyvale, CA

Thermal Tool Requirements and the 1997 National Technology Roadmap for Semiconductors.

D. Lindholm, SEMATECH, Austin, TX

 

ADVANCED RTP AND FURNACE TECHNOLOGIES

 

Advanced Technologies for Rapid Thermal Oxidation

G. Miner, G. Xing, D. Lopes, R. Bar-Gadda, Applied Materials, Santa Clara, CA

RTP Development Requirements

Z. Nenyei, G. Wein, W. Lerch, C. Grunwald, J. Gelpey, STEAG-AST Elektronik, Germany, S. Wallmuller, Institute for Laser Technologies, Ulm, Germany

Real-Time Emissivity and Temperature Estimation for a Rapid Thermal Processing Using Advanced Filtering Technique

S. Belikov, B. Friedland, New Jersey Institute of Technology, Newark, NJ, J. Kamali, CVC Products, Fremont, CA

A Fast Ramping Batch Processor for Diffusion and Oxidation Applications

C. Ratliff, C. Porter, A. Laser, SVG THERMCO, San Jose, CA, A. Dip, Motorola, Austin, TX

Rapid Thermal Annnealing of Low Energy As+ Implants.

S. D. Markus, STEAG-AST Elektronik, Tempe, AZ, D.F. Downey, S. L. Daryanani, J. W. Chow, Varian, Gloucester, MA

DRAM Capacitor Formation with Selective HSG from a Vertical UHV Furnace System

C. Werkhoven, H. de Waard, T. Yoshida , C.E. Merrittt, Y. Mori, A. Shimizu, M. Mansoori, ASM, Phoenix, AZ

Optimization of the RTP Annealing of Low Energy BF2 and B Implants

S. Toodrov, D. F. Downey, S.L. Daryanani, J. Chow, M. Meloni, Varian, Gloucester, MA, S.D. Markus, STEAG-AST Elektronik, Tempe, AZ

 

TEMPERATURE PHENOMENA

 

Characteristic Identification of Optical Pyrometers in RTP Systems

J. Kamali, Y.J. Lee, CVC Products, Fremont, CA, S. Belikov, New Jersey Institute of Technology, Newark, NJ

RTP: Study of Some Critical Parameters for DRAM

R.A. Weimer, D. Ratakonda, C. Powell, M. Nuttall, R.P.S. Thakur, Micron Technology, Boise, ID, P.J. Timans, N. Shah, AG Associates, San Jose, CA

Novel Approach to Temperature Calibration on the RTP Centura102

M. Yam, A. Rubinchik, B. Peuse, Applied Materials, Santa Clara, CA

Platinum-Palladium Thin Film Thermocouples for Temperature Measurements on Silicon Wafer

K.G. Kreider, F. DiMeo, NIST Gaithersburg, MD

Rapid Thermal CVD with Emissivity-Independent Temperature Sensing System

Z. Atzmon, Z. Doitel, A. Harnik, S. Levi, A. Thon, P. Alezra, H. Gilboa, AG Associates, Israel

A Simple Method of Controlling Wafer Temperature in Rapid Thermal Process

A. See, H. Wong, Y.S. Lu, Chartered Semiconductor, Singapore, L.H. Chua, STEAG AST Elektronik, Singapore

Temperature Degradation Caused by BPSG Reflow in an RTP System

R. Schenk, V. Sargunas, R. Piotrowski, SGS-Thompson, Phoenix, AZ

 

ADVANCED PROCESSING I

 

Manufacturability of Rapid Thermal N2O Oxynitridation for Ultrathin Gate Dielectrics in 0.25 mm CMOS Process and Beyond

S.P. Tay, Y.Z. Hu, Y. Wasserman, AG Associates, San Jose, CA

Growth of Ultra Thin Gate Oxide Films using Fast Thermal Processing

M. Imai, N. Noro, T. Kakuta, S. Kaushal, T. Tsuda, Tokyo Electron, Japan, D. Marks, S. Kaushal, Tokyo Electron America, Austin, TX

EEPROM Gate-stack Process on a Hot Cluster Tool

A. Grassl, A. Geschwandtner, A. Talg, G. Innertsberger, A. Mattheus, Siemens, Munich, Germany

Thickness Uniformity and Interfacial Roughness of Ultra-thin Rapid Thermal Oxides Grown in a Cluster Tool

T.W. Sorsch, F. Baumann, M.L. Green, J.M. Rosamilia, J. Sapjeta, P.J. Silverman, G.L. Timp, B. Weir, Lucent Technologies, Murray Hill, NJ

The Study of N2O Oxidation Uniformities of RTP Centura Rapid Thermal Processor

G.C. Xing, D. Lopes, G.E. Miner, Applied Materials, Santa Clara, CA

 

TEMPERATURE MEASUREMENT AND EMISSIVITY

 

Temperature and Wavelength Dependent Emissivity of Silicon Related Materials

S. Abedrabbo, N.M. Ravindra , O.H. Gokce, F.M. Tong, M. Beggans, A. Patel, V. Rajsekhar, D. Pattnaik, New Jersey Institute of Technology, Newark, NJ, A. Nanda, Lucent Technologies, Orlando, FL, A.T. Fiory, Lucent Technology, Murray Hill, NJ, M. Yam, P. Peuse, Applied Materials, Santa Clara, CA

Temperature Dependent Emissivity of Non-Silicon Materials

N.M. Ravindra, O.H. Gokce, F.M. Tong, S. Abedrabbo, S. Amin, A. Patel, V. Rajasekhar, New Jersey Institute of Technology, Newark, NJ, K. Linga, C.S. Wang, Epitaxx, West Trenton, NJ, I. Ferguson, Emcore, Somerset, NJ, F. Roozeboom, Philips, Eindhoven, The Netherlands

Emissivity-Independent Temperature Control During Phase Transition in Rapid Thermal Processing

M. Oh, S.M. Merchant, B. Nquyenphu, Lucent Technologies, Orlando, FL

In-Situ Wafer Emissivity Measurement in a Furnace Heated RTP System

J. Hebb, Eaton Corp., Peabody, MA, C. Schietinger, Luxtron, Portland, OR

Wafer-Free Qualification of Rapid Thermal Processor

R. Widenhofer, S.K. Pozder, Motorola, Austin, TX, S.D. Markus, STEAG AST Elektronik

Effect of Varying Emissivity During Titanium Silicidation on RTP Temperature Control

D. Jennings, Applied Materials, Santa Clara, CA

 

RAPID THERMAL CVD

 

Integrated Processing for FOEL in Advanced DRAM and Flash Devices Using RT-CVD Cluster Tool

H. Gilboa, P. Alazera, R. Koriat, AG Associates, Israel

Transient Thermal and Stress Analysis of the APCVD Reactor During Fast Heat-Up

V.V. Kudriavtsev, Watkins-Johnson Co., Scotts Valley, CA, W. Cheng, FMC Corp., M. Refai, ISI, Santa Clara, CA, M. Rist, CFD Research Corp. Huntsville, AL

The Deposition of In-Situ Doped Silicon and Silicon Germanium in a Single Wafer RTCVD System

I. Raaijmakers, D. Mayer, J. Italiano, ASM, Phoenix, AZ

Analysis of Heat and Mass Transfer in RTPCVD Reactor

A. Thon, G. Kohav, V. Klozner, Z. Atzmon, S. Levy, H. Gilboa, AG Associates, Israel

Numerical Study of TEOS/O3 CVD Mechanism in an Industrial Reactor

N. Zhou, A. Krishnan, CFD Research, Huntsville, AL, V. Kudriavtsev, Watkins-Johnson Co., Scotts Valley, CA

RTP-MOCVD of Epitaxial II-VI Semiconductors

S. Stolyarova, N. Amir, Y. Nemirovsky, Technion University, Israel

 

MODELING AND SIMULATION

 

Efficient CFD Modeling of Single Wafer Systems for Closed Loop Evaluation

J.L. Ebert, G.W. van der Linden, R.L. Kosut, A. Emami-Naeini, SC Solution, Santa Clara, CA

Computationally Efficient Simulation of Atmospheric Pressure Furnace Processes

J.V. Cole, E.W. Egan, Motorola, Austin, TX

General Analysis Techniques for Design of Thermal Processing Equipment

K. Knutson, S. Shankar, Intel, Portland, OR

Optimization of Wafer Temperature-Uniformity with Application to a RTO Chember

T. Schafbauer, A. Kersch, Siemens, Germany

A Robust RTP Chamber Model for Study of Wafer and Quartz Temperature

J. G. Li, R. Champetier, P.J. Timans, AG Associates, San Jose, CA,

Power Controlled Open-loop Performance in Production

R. Hayn, A. Tillmann, STEAG-AST Elektronik, Dornstadt, Germany, W. Kegel, Siemens, Dresden, Germany

 

MARKETING PRESENTATION

 

How is the RTP Market Evolving ?

J.M. Salzer, Salzer Technology, Santa Monica, CA

EATON 300mm Thermal Processing System "Summit 300"

W. Bintz, L. Bourget, W. Drislane, D. Rodier, Eaton, Peabody, MA

The STEAG AST SHS-3000: An Advanced RTP Tool for 200 and 300 mm

J. Gelpey, R. Hollands, STEAG AST Elektronik, Tempe, A. Tillmann, P. Munzinger, STEAG AST Elektronik, Dornstadt, Germany

 

TEMPERATURE MEASUREMENT & RTP EQUIPMENT

 

A Review of Wafer Temperature Measurement Using Optical Fibers and Ripple Pyrometry

C. Schietinger, B. Adams, Luxtron Corp., Santa Clara, CA

In-Chamber Thermometry Calibration Using a Silicon Proof Wafer

B.K.Tsai, F.J. Lovas, D.P. DeWitt, K.G. Kreider, G.W. Burns, D.W. Allen NIST, Gaithersburg, MD

Ripple Pyrometry in Manufacturing Environment

B. Nguyenphu, M. Oh, Lucent Technologies, Orlando, FL

Advances in Temperature Measurement and Control for RTP

B. Peuse, M. Yam, S. Bahl, Applied Materials, Santa Clara, CA, C. Elia, Oakleaf Engineering, Redwood City, CA

Maintaining +/- 3 oC RTP Temperature Control for Ion Implanted GaAs Anneal Processing

H. Francz, M. Wilson, A. Hoover, C. Coffman, Motorola, Tempe, AZ

Furnace Insulation Modules - A Unique Insulation and Heating System for RTP of Semiconductors Materials

D.P. Hamling, ZIRCAR Products, FL

Sealing Technology

D. Vernikovsky, Greene, Tweed & Co., San Jose, CA

 

ADVANCED PROCESSING II

 

Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides

J. Kuehne, S. Hattangady, Texas Instruments, Dallas, J. Piccirillo, G. Xing, G. Miner, D. Lopes, Applied Materials, Santa Clara, CA

Defect Control of Silicon Wafers During Rapid Thermal Processing in a Lamp-Free Environment: X-Ray and Lifetime Imaging

A. Karaoui, Q. Zhong, A. Romanovski, G. Rozgonyi, North Carolina State University, Raleigh, NC, P. Rooshbrook, S. Savas, Mattson Technology, Fremont, CA

Process Integration for Fabricating Silicide Contacts and Raise Shallow Junctions via Rapid Thermal Processing

W. Zagodzon-Wosik, S.R. Gooty, I. Rusakova, Z.H. Zhang, D. Marton, T. Lin, D.X. Zhang, University of Houston, TX, R.J. Bleiler, Evans Texas, Austin, TX

Effects of Annealing on W-Si-N/Si02/Si Structures

O.H. Gokce, S. Amin, A. Patel, V. Rajsekhar, S. Abedrabbo, N.M. Ravindra, New Jersey Institute of Technology, Newark, NJ, J.G. Fleming, Sandia Nat. Lab. Albuquerque, NM, P.J. Zanzucchi, R.J. Pfaff, D.J. Szostak, Sarnoff Corp., Princeton, NJ

RTA and Activation Mechanism of Low Energy Si-Implanted Layer on GaAs Substrate

T. Taniguchi, Japan Radio, Co., Japan

Compatibility of RTP Nickel Silicidation in the Self-Aligned Silicide Process for Sub-Quarter Micron ULSI

Y.Z. Hu, S.P. Tay, Y. Wasserman, AG Associates, San Jose, CA

Reduction in Contact Resistivity Between Si-Substrate and Poly-Si Interface Using FTPS

H. Igekawa, K. Maekawa, , M. Imai, T. Nishimura, R. Niino, TEL Japan, D. Marks, S. Kaushal, TEL, Austin, TX